From a8e89afb4fcd494f9feee75c2b3fc1d60e100cb5 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Mon, 5 Nov 2018 16:19:15 +0100 Subject: [PATCH 01/14] PRJ: bump version to v3.1.2.dev0 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 94ff29cc4..0e6b5ab95 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -3.1.1 +3.1.2.dev0 From 4ab111080b454cac019f06129cd82679bdd72ee0 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Tue, 6 Nov 2018 11:55:04 +0100 Subject: [PATCH 02/14] MAINT: remove pywin32 from appveyor (installed by default in recent Anaconda Python) --- appveyor.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/appveyor.yml b/appveyor.yml index b0fad4746..49df83651 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -20,7 +20,7 @@ install: - conda update --all --yes - conda info -a - conda install --yes bitarray cython ipython matplotlib mock nose numba numpy pyqt pyserial pytables pyyaml pyzmq qtpy scipy - - conda install --yes pywin32 + #- conda install --yes pywin32 - pip install progressbar-latest pyvisa pyvisa-py git+https://github.com/pyqtgraph/pyqtgraph.git@pyqtgraph-0.10.0 #git+https://github.com/uvemas/ViTables@develop # test packages required for USB interface - pip install pyusb From 7b070e73efb03cda608513f1e4402fea00682d17 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Tue, 6 Nov 2018 12:55:51 +0100 Subject: [PATCH 03/14] MAINT: remove pywin32 --- README.md | 5 ----- appveyor.yml | 1 - 2 files changed, 6 deletions(-) diff --git a/README.md b/README.md index ceea0d56f..9cd1598bb 100644 --- a/README.md +++ b/README.md @@ -61,11 +61,6 @@ Run the **following commands** to install the packages: pip install progressbar-latest pyvisa pyvisa-py git+https://github.com/pyqtgraph/pyqtgraph.git@pyqtgraph-0.10.0 ``` -On Windows, the `pywin32` package is required: - ``` - conda install pywin32 - ``` - [Basil](https://github.com/SiLab-Bonn/basil) (>=2.4.12,<3.0.0) is required: ``` pip install "basil_daq>=2.4.12,<3.0.0" diff --git a/appveyor.yml b/appveyor.yml index 49df83651..790f19c4c 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -20,7 +20,6 @@ install: - conda update --all --yes - conda info -a - conda install --yes bitarray cython ipython matplotlib mock nose numba numpy pyqt pyserial pytables pyyaml pyzmq qtpy scipy - #- conda install --yes pywin32 - pip install progressbar-latest pyvisa pyvisa-py git+https://github.com/pyqtgraph/pyqtgraph.git@pyqtgraph-0.10.0 #git+https://github.com/uvemas/ViTables@develop # test packages required for USB interface - pip install pyusb From 6ce36b77f0606aa739b3b7a9aa5c352f239852bb Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Tue, 6 Nov 2018 13:17:01 +0100 Subject: [PATCH 04/14] PRJ: remove deprecated configuration files --- pybar/dut_configuration_lx9.yaml | 15 -- pybar/dut_configuration_mio_gpac.yaml | 28 --- ...guration_mmc3_8chip_multi_tx_eth_SHiP.yaml | 190 ------------------ pybar/dut_configuration_mmc3_beast_eth.yaml | 74 ------- pybar/dut_lx9.yaml | 33 --- pybar/dut_mio_gpac.yaml | 130 ------------ pybar/dut_mmc3_beast_eth.yaml | 109 ---------- 7 files changed, 579 deletions(-) delete mode 100644 pybar/dut_configuration_lx9.yaml delete mode 100644 pybar/dut_configuration_mio_gpac.yaml delete mode 100644 pybar/dut_configuration_mmc3_8chip_multi_tx_eth_SHiP.yaml delete mode 100644 pybar/dut_configuration_mmc3_beast_eth.yaml delete mode 100644 pybar/dut_lx9.yaml delete mode 100644 pybar/dut_mio_gpac.yaml delete mode 100644 pybar/dut_mmc3_beast_eth.yaml diff --git a/pybar/dut_configuration_lx9.yaml b/pybar/dut_configuration_lx9.yaml deleted file mode 100644 index ab5d20e8c..000000000 --- a/pybar/dut_configuration_lx9.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# LX9 board -ETH: - ip : "192.168.10.11" - udp_port : 4660 - tcp_port : 24 - tcp_connection : True - tcp_to_bus : False - -# FE-I4 command ouput -CMD_CH0: - OUTPUT_MODE : 0 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -# FE-I4 data receiver -DATA_CH0: - INVERT_RX : 0 diff --git a/pybar/dut_configuration_mio_gpac.yaml b/pybar/dut_configuration_mio_gpac.yaml deleted file mode 100644 index 140ca675e..000000000 --- a/pybar/dut_configuration_mio_gpac.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# USBpix board -USB: - bit_file : "firmware/mio_gpac.bit" # Selecting FPGA firmware - board_id : # Selecting USBpix board by ID - avoid_download : True # Avoiding download of FPGA firmware if already initialized - -# Trigger -TRIGGER_FEI4: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 0 # Selecting trigger input: CCPD Monitor from GPAC (8), RX2 (TDC loop-through) (4), RX0 (2), MonHit/HitOR from GPAC (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: CCPD Monitor from GPAC (8), RX2 (TDC loop-through) (4), RX0 (2), MonHit/HitOR from GPAC (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX1 (2), RX FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # increase minimum trigger length - TRIGGER_DATA_DELAY : 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length - DATA_FORMAT : 0 # trigger number according to TRIGGER_MODE (0), time stamp only (1), combined, 15bit time stamp + 16bit trigger number (2) - -# TDC for high precision charge measurements -TDC_RX2: - EN_WRITE_TIMESTAMP : 0 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -# FE-I4 command output -CMD_FEI4: - OUTPUT_MODE : 0 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) diff --git a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth_SHiP.yaml b/pybar/dut_configuration_mmc3_8chip_multi_tx_eth_SHiP.yaml deleted file mode 100644 index 0833300f6..000000000 --- a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth_SHiP.yaml +++ /dev/null @@ -1,190 +0,0 @@ -# MMC3 board with max. 8 FEI4s with multiple TX -ETH: - ip : "192.168.10.11" - udp_port : 4660 - tcp_port : 24 - tcp_connection : True - tcp_to_bus : False - -# Trigger -TRIGGER_CH0: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 512 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), LEMO RX0 synced with ext. trigger clock (512), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 1 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - USE_EXT_TIMESTAMP : 1 # if (1) the internal 31bit timestamp is replaced by a timestamp based on an external (40MHz) clock at LEMO RX1. Needs Trigger select 512 - -TRIGGER_CH1: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 4 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -TRIGGER_CH2: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 8 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -TRIGGER_CH3: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 16 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - USE_EXT_TIMESTAMP : 1 # if (1) the internal 31bit timestamp is replaced by a timestamp based on an external clock at LEMO RX1 - -TRIGGER_CH4: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 32 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -TRIGGER_CH5: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 64 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -TRIGGER_CH6: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 128 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -TRIGGER_CH7: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 256 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -# TDC for high precision charge measurements -TDC_CH0: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH1: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH2: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH3: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH4: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH5: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH6: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -# FE-I4 command output -CMD_CH0: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH1: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH2: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH3: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH4: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH5: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH6: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -CMD_CH7: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -# FE-I4 data receivers -DATA_CH0: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH1: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH2: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH3: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH4: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH5: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH6: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH7: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) diff --git a/pybar/dut_configuration_mmc3_beast_eth.yaml b/pybar/dut_configuration_mmc3_beast_eth.yaml deleted file mode 100644 index 32b71fb52..000000000 --- a/pybar/dut_configuration_mmc3_beast_eth.yaml +++ /dev/null @@ -1,74 +0,0 @@ -# MMC3 board supporting BEAST/FANGS -ETH: - ip : "192.168.10.11" - udp_port : 4660 - tcp_port : 24 - tcp_connection : True - tcp_to_bus : False - -# Trigger -TRIGGER_CH0_TO_CH4: - TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) - TRIGGER_SELECT : 62 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4 (2/4/8/16/32), LEMO RX0 (1), disabled (0) - TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4 (2/4/8/16/32), LEMO RX0 (1), disabled (0) - TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4 full (2/4/8/16/32), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) - TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) - -# TDC for high precision charge measurements -TDC_CH0: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH1: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH2: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH3: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -TDC_CH4: - EN_WRITE_TIMESTAMP : 1 # Writing trigger timestamp - EN_TRIGGER_DIST : 0 # Measuring trigger to TDC delay with 640MHz clock - EN_NO_WRITE_TRIG_ERR : 0 # Writing TDC word only if valid trigger occurred - EN_INVERT_TDC : 0 # Inverting TDC input - EN_INVERT_TRIGGER : 0 # Inverting trigger input - -# FE-I4 command output -CMD_CH0_TO_CH4: - OUTPUT_MODE : 3 # Selecting command output mode: positive edge (0), negative edge (1), Manchester Code according to IEEE 802.3 (2), Manchester Code according to G.E. Thomas (3) - -# FE-I4 data receiver -DATA_CH0: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH1: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH2: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH3: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) - -DATA_CH4: - INVERT_RX : 0 # Inverting data input: disabled (0), enabled (e.g. for DBM modules) (1) diff --git a/pybar/dut_lx9.yaml b/pybar/dut_lx9.yaml deleted file mode 100644 index f4307a1d6..000000000 --- a/pybar/dut_lx9.yaml +++ /dev/null @@ -1,33 +0,0 @@ -# -# ------------------------------------------------------------ -# Copyright (c) All rights reserved -# SiLab, Institute of Physics, University of Bonn -# ------------------------------------------------------------ -# - -name : lx9 -version : 0.1 - -transfer_layer: - - name : ETH - type : SiTcp - -hw_drivers: - - name : CMD_CH0 - type : cmd_seq - interface : ETH - base_addr : 0x0000 - - - name : SITCP_FIFO - type : sitcp_fifo - interface : ETH - - - name : DATA_CH0 - type : fei4_rx - interface : ETH - base_addr : 0x8600 - - - name : I2C - type : i2c - interface : ETH - base_addr : 0x8800 diff --git a/pybar/dut_mio_gpac.yaml b/pybar/dut_mio_gpac.yaml deleted file mode 100644 index 6956d0d8e..000000000 --- a/pybar/dut_mio_gpac.yaml +++ /dev/null @@ -1,130 +0,0 @@ - -name : mio_gpac -version : 2.0.0 - -transfer_layer: - - name : USB - type : SiUsb - -hw_drivers: - - name : GPAC_ADAPTER_CARD - type : GPAC - interface : USB - base_addr : 0x0 - - - name : CMD_FEI4 - type : cmd_seq - interface : USB - base_addr : 0x10000 - - - name : SRAM_FIFO - type : sram_fifo - interface : USB - base_addr : 0x18100 - base_data_addr : 0x0001000000000000 - - - name : TRIGGER_FEI4 - type : tlu - interface : USB - base_addr : 0x18200 - - - name : FEI4_RX - type : fei4_rx - interface : USB - base_addr : 0x18300 - - - name : TDC_RX2 - type : tdc_s3 - interface : USB - base_addr : 0x18700 - - - name : GPIO_ENABLE_CHANNEL - type : gpio - interface : USB - base_addr : 0x18800 - -# - name : GPAC_SPI -# type : spi -# interface : USB -# base_addr : 0x18900 -# mem_bytes : 2 - -# - name : GPAC_ADC -# type : fadc_rx -# interface : USB -# base_addr : 0x18940 - -# - name : GPAC_ADC_1 -# type : fadc_rx -# interface : USB -# base_addr : 0x18950 - - - name : CCPD_GLOBAL_SPI - type : spi - interface : USB - base_addr : 0x18980 - mem_bytes : 15 - - - name : CCPD_CONFIG_SPI - type : spi - interface : USB - base_addr : 0x19000 - mem_bytes : 54 - - - name : CCPD_TDCGATE_PULSE - type : pulse_gen - interface : USB - base_addr : 0x18A00 - - - name : CCPD_INJ_PULSE - type : pulse_gen - interface : USB - base_addr : 0x18A80 - - - name : CCPD_TDC - type : tdc_s3 - interface : USB - base_addr : 0x19100 - -registers: - - name : ENABLE_CHANNEL - type : StdRegister - hw_driver : GPIO_ENABLE_CHANNEL - size : 8 - fields: - - name : CCPD_TDC - size : 1 - offset : 3 - - name : TDC - size : 1 - offset : 2 - - name : TLU - size : 1 - offset : 1 - - name : FE - size : 1 - offset : 0 - - - name : CCPD_Vdd - type : FunctionalRegister - hw_driver : GPAC_ADAPTER_CARD - arg_names : [value] - arg_add : {'channel': 'PWR0'} - - - name : V_in - type : FunctionalRegister - hw_driver : GPAC_ADAPTER_CARD - arg_names : [value] - arg_add : {'channel': 'PWR1'} - - - name : CCPD_Vssa - type : FunctionalRegister - hw_driver : GPAC_ADAPTER_CARD - arg_names : [value] - arg_add : {'channel': 'PWR2'} - - - name : CCPD_VGate - type : FunctionalRegister - hw_driver : GPAC_ADAPTER_CARD - arg_names : [value] - arg_add : {'channel': 'PWR3'} diff --git a/pybar/dut_mmc3_beast_eth.yaml b/pybar/dut_mmc3_beast_eth.yaml deleted file mode 100644 index 23bed7b24..000000000 --- a/pybar/dut_mmc3_beast_eth.yaml +++ /dev/null @@ -1,109 +0,0 @@ -# -# ------------------------------------------------------------ -# Copyright (c) All rights reserved -# SiLab, Institute of Physics, University of Bonn -# ------------------------------------------------------------ -# -# MMC3 board supporting BEAST/FANGS - -name : mmc3_beast_eth -version : 0.1 - -transfer_layer: - - name : ETH - type : SiTcp - -hw_drivers: - - name : TRIGGER_CH0_TO_CH4 - type : tlu - interface : ETH - base_addr : 0x8200 - - - name : CMD_CH0_TO_CH4 - type : cmd_seq - interface : ETH - base_addr : 0x0000 - - - name : DATA_CH0 - type : fei4_rx - interface : ETH - base_addr : 0x9000 - - - name : DATA_CH1 - type : fei4_rx - interface : ETH - base_addr : 0x9100 - - - name : DATA_CH2 - type : fei4_rx - interface : ETH - base_addr : 0x9200 - - - name : DATA_CH3 - type : fei4_rx - interface : ETH - base_addr : 0x9300 - - - name : DATA_CH4 - type : fei4_rx - interface : ETH - base_addr : 0x9400 - - - name : SITCP_FIFO - type : sitcp_fifo - interface : ETH - - - name : TDC_CH0 - type : tdc_s3 - interface : ETH - base_addr : 0xa000 - - - name : TDC_CH1 - type : tdc_s3 - interface : ETH - base_addr : 0xa100 - - - name : TDC_CH2 - type : tdc_s3 - interface : ETH - base_addr : 0xa200 - - - name : TDC_CH3 - type : tdc_s3 - interface : ETH - base_addr : 0xa300 - - - name : TDC_CH4 - type : tdc_s3 - interface : ETH - base_addr : 0xa400 - - - name : DLY_CONFIG_GPIO - type : gpio - interface : ETH - base_addr : 0xb000 - size : 48 - -registers: - - name : DLY_CONFIG - type : StdRegister - hw_driver : DLY_CONFIG_GPIO - size : 48 - fields : - - name : CLK_DLY - offset : 42 - size : 3 - - name : RX - offset : 39 - size : 8 - repeat : 5 - fields : - - name : LD - size : 1 - offset : 7 - - name : INV - size : 1 - offset : 6 - - name : DLY - size : 5 - offset : 4 From f81aa569f09bddf4d97eda8e2fba8cab412de5cb Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Tue, 6 Nov 2018 13:25:27 +0100 Subject: [PATCH 05/14] MAINT: update comments in yaml files --- pybar/dut_configuration_mio.yaml | 4 +-- ...onfiguration_mmc3_16chip_multi_tx_eth.yaml | 32 +++++++++---------- pybar/dut_configuration_mmc3_8chip_eth.yaml | 4 +-- ...configuration_mmc3_8chip_multi_tx_eth.yaml | 32 +++++++++---------- 4 files changed, 36 insertions(+), 36 deletions(-) diff --git a/pybar/dut_configuration_mio.yaml b/pybar/dut_configuration_mio.yaml index c768771ca..c0b2f7156 100644 --- a/pybar/dut_configuration_mio.yaml +++ b/pybar/dut_configuration_mio.yaml @@ -16,9 +16,9 @@ TRIGGER_CH1_TO_CH4: TRIGGER_SELECT : 0 # Selecting trigger input: RX2 (TDC loop-through) (8), RX1 (4), RX0 (2), MonHit/HitOR from Adapter Card (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: RX2 (TDC loop-through) (8), RX1 (4), RX0 (2), MonHit/HitOR from Adapter Card (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX1 (2), RX FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # increase minimum trigger length + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # trigger number according to TRIGGER_MODE (0), time stamp only (1), combined, 15bit time stamp + 16bit trigger number (2) # TDC for high precision charge measurements diff --git a/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml b/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml index 71a5fecfb..8fe5ad24f 100644 --- a/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml +++ b/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml @@ -12,9 +12,9 @@ TRIGGER_CH0: TRIGGER_SELECT : 2 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH1: @@ -22,9 +22,9 @@ TRIGGER_CH1: TRIGGER_SELECT : 4 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH2: @@ -32,9 +32,9 @@ TRIGGER_CH2: TRIGGER_SELECT : 8 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH3: @@ -42,9 +42,9 @@ TRIGGER_CH3: TRIGGER_SELECT : 16 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH4: @@ -52,9 +52,9 @@ TRIGGER_CH4: TRIGGER_SELECT : 32 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH5: @@ -62,9 +62,9 @@ TRIGGER_CH5: TRIGGER_SELECT : 64 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH6: @@ -72,9 +72,9 @@ TRIGGER_CH6: TRIGGER_SELECT : 128 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH7: @@ -82,9 +82,9 @@ TRIGGER_CH7: TRIGGER_SELECT : 256 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) # TDC for high precision charge measurements diff --git a/pybar/dut_configuration_mmc3_8chip_eth.yaml b/pybar/dut_configuration_mmc3_8chip_eth.yaml index 4d0434cb1..92c7fe248 100644 --- a/pybar/dut_configuration_mmc3_8chip_eth.yaml +++ b/pybar/dut_configuration_mmc3_8chip_eth.yaml @@ -12,9 +12,9 @@ TRIGGER_CH0_TO_CH7: TRIGGER_SELECT : 1 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) # TDC for high precision charge measurements diff --git a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml b/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml index 2bc0096bd..c76a4ba6f 100644 --- a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml +++ b/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml @@ -12,9 +12,9 @@ TRIGGER_CH0: TRIGGER_SELECT : 1 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH1: @@ -22,9 +22,9 @@ TRIGGER_CH1: TRIGGER_SELECT : 4 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH2: @@ -32,9 +32,9 @@ TRIGGER_CH2: TRIGGER_SELECT : 8 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH3: @@ -42,9 +42,9 @@ TRIGGER_CH3: TRIGGER_SELECT : 16 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH4: @@ -52,9 +52,9 @@ TRIGGER_CH4: TRIGGER_SELECT : 32 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH5: @@ -62,9 +62,9 @@ TRIGGER_CH5: TRIGGER_SELECT : 64 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH6: @@ -72,9 +72,9 @@ TRIGGER_CH6: TRIGGER_SELECT : 128 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) TRIGGER_CH7: @@ -82,9 +82,9 @@ TRIGGER_CH7: TRIGGER_SELECT : 256 # Selecting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_INVERT : 0 # Inverting trigger input: MonHit/HitOR from module 0/1/2/3/4/5/6/7 (2/4/8/16/32/64/128/256), LEMO RX0 (1), disabled (0) TRIGGER_VETO_SELECT : 1 # Selecting trigger veto: RX FIFO 0/1/2/3/4/4/6/7 full (2/4/8/16/32/64/128/256), FIFO full (1), disabled (0) - TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Increasing minimum trigger length in TLU data handshale mode (preventing certain TLU flaws) + TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) - TRIGGER_THRESHOLD : 0 # Standard trigger minimum length in clock cycles of the trigger/TLU FSM + TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) # TDC for high precision charge measurements From 642228034d8af8929f4d6895382fc2041278b167 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Tue, 6 Nov 2018 13:40:14 +0100 Subject: [PATCH 06/14] MAINT: update comments in yaml files --- pybar/dut_configuration_mio.yaml | 2 +- ...t_configuration_mmc3_16chip_multi_tx_eth.yaml | 16 ++++++++-------- pybar/dut_configuration_mmc3_8chip_eth.yaml | 2 +- ...ut_configuration_mmc3_8chip_multi_tx_eth.yaml | 16 ++++++++-------- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/pybar/dut_configuration_mio.yaml b/pybar/dut_configuration_mio.yaml index c0b2f7156..f366e2042 100644 --- a/pybar/dut_configuration_mio.yaml +++ b/pybar/dut_configuration_mio.yaml @@ -19,7 +19,7 @@ TRIGGER_CH1_TO_CH4: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # trigger number according to TRIGGER_MODE (0), time stamp only (1), combined, 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) # TDC for high precision charge measurements TDC_RX2: diff --git a/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml b/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml index 8fe5ad24f..266c189fc 100644 --- a/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml +++ b/pybar/dut_configuration_mmc3_16chip_multi_tx_eth.yaml @@ -15,7 +15,7 @@ TRIGGER_CH0: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH1: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -25,7 +25,7 @@ TRIGGER_CH1: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH2: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -35,7 +35,7 @@ TRIGGER_CH2: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH3: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -45,7 +45,7 @@ TRIGGER_CH3: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH4: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -55,7 +55,7 @@ TRIGGER_CH4: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH5: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -65,7 +65,7 @@ TRIGGER_CH5: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH6: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -75,7 +75,7 @@ TRIGGER_CH6: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH7: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -85,7 +85,7 @@ TRIGGER_CH7: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) # TDC for high precision charge measurements TDC_CH0: diff --git a/pybar/dut_configuration_mmc3_8chip_eth.yaml b/pybar/dut_configuration_mmc3_8chip_eth.yaml index 92c7fe248..38699e2d6 100644 --- a/pybar/dut_configuration_mmc3_8chip_eth.yaml +++ b/pybar/dut_configuration_mmc3_8chip_eth.yaml @@ -15,7 +15,7 @@ TRIGGER_CH0_TO_CH7: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) # TDC for high precision charge measurements TDC_CH0: diff --git a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml b/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml index c76a4ba6f..36418083d 100644 --- a/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml +++ b/pybar/dut_configuration_mmc3_8chip_multi_tx_eth.yaml @@ -15,7 +15,7 @@ TRIGGER_CH0: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH1: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -25,7 +25,7 @@ TRIGGER_CH1: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH2: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -35,7 +35,7 @@ TRIGGER_CH2: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH3: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -45,7 +45,7 @@ TRIGGER_CH3: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH4: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -55,7 +55,7 @@ TRIGGER_CH4: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH5: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -65,7 +65,7 @@ TRIGGER_CH5: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH6: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -75,7 +75,7 @@ TRIGGER_CH6: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) TRIGGER_CH7: TRIGGER_MODE : 0 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3) @@ -85,7 +85,7 @@ TRIGGER_CH7: TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES : 3 # Minimum TLU trigger length (TLU data handshale mode) required for accepting the trigger (preventing certain EUDAQ TLU firmware flaws) TRIGGER_DATA_DELAY : 8 # TLU data handshake data delay depends on the cable length and should be adjusted with a delay scan (run scan/tune_tlu.py) TRIGGER_THRESHOLD : 0 # Minimum trigger length (standard trigger and TLU no handshake mode) required for accepting the trigger - DATA_FORMAT : 0 # 31bit trigger number according to TRIGGER_MODE (0), 31bit time stamp (1), 15bit time stamp + 16bit trigger number (2) + DATA_FORMAT : 0 # 31bit trigger number (0), 31bit time stamp (1), combined (15bit time stamp + 16bit trigger number) (2) # TDC for high precision charge measurements TDC_CH0: From cb8817c0b9b3f66ba6b861968f69a92542e7f1ef Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 10:35:21 +0100 Subject: [PATCH 07/14] ENH: prevent building event from data before first trigger word and wait for TLU to stop sending triggers before stopping run --- pybar/scans/scan_eudaq_ext_trigger.py | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index 956828450..ac845658b 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -42,11 +42,12 @@ def scan(self): self.last_trigger_number = None # set TLU max trigger counter self.max_trigger_counter = 2 ** 15 + self.max_trigger_counter_bits = 2 ** np.int(np.ceil(np.log2(self.max_trigger_counter))) - 1 start = time() lvl1_command = self.register.get_commands("zeros", length=self.trigger_delay)[0] + self.register.get_commands("LV1")[0] + self.register.get_commands("zeros", length=self.trigger_rate_limit)[0] self.register_utils.set_command(lvl1_command) - - self.remaining_data = np.ndarray((0,), dtype=np.uint32) + last_number_of_triggers = None + self.remaining_data = np.zeros((0,), dtype=np.uint32) # initialize array of zero length with self.readout(no_data_timeout=self.no_data_timeout, **self.scan_parameters._asdict()): with self.trigger(): @@ -63,9 +64,15 @@ def scan(self): logging.info('Runtime: %s\nTriggers: %d\nData words/s: %s\n' % (strftime('%H:%M:%S', gmtime(time() - start)), triggers, str(data_words))) if self.max_triggers and triggers >= self.max_triggers: self.stop(msg='Trigger limit was reached: %i' % self.max_triggers) + if last_number_of_triggers is not None or pp.StoppingRun: # stopping EUDAQ run + if last_number_of_triggers is None: + last_number_of_triggers = self.dut['TLU']['TRIGGER_COUNTER'] + elif last_number_of_triggers == self.dut['TLU']['TRIGGER_COUNTER']: # trigger number not increased, TLU has stopped + break # leave scan loop if self.remaining_data.shape[0] > 0: - pp.SendEvent(self.remaining_data) + pp.SendEvent(self.remaining_data) # send remaining event + self.remaining_data = self.remaining_data[:0] # make remaining data array empty logging.info('Total amount of triggers collected: %d', self.dut['TLU']['TRIGGER_COUNTER']) @@ -86,7 +93,7 @@ def handle_data(self, data, new_file=False, flush=True): if self.remaining_data.shape[0] > 0: # check trigger number if is_trigger_word(self.remaining_data[0]): - trigger_number = self.remaining_data[0] & (self.max_trigger_counter - 1) + trigger_number = np.bitwise_and(self.remaining_data[0], self.max_trigger_counter_bits) if self.last_trigger_number is not None and ((self.last_trigger_number + 1 != trigger_number and self.last_trigger_number + 1 != self.max_trigger_counter) or (self.last_trigger_number + 1 == self.max_trigger_counter and trigger_number != 0)): if self.data_error_occurred: if trigger_number > self.last_trigger_number: @@ -95,15 +102,18 @@ def handle_data(self, data, new_file=False, flush=True): missing_trigger_numbers = self.max_trigger_counter - (self.last_trigger_number - trigger_number) - 1 logging.warning('Data errors detected: trigger number read: %d, expected: %d, sending %d empty events', trigger_number, 0 if (self.last_trigger_number + 1 == self.max_trigger_counter) else (self.last_trigger_number + 1), missing_trigger_numbers) for missing_trigger_number in range(self.last_trigger_number + 1, self.last_trigger_number + missing_trigger_numbers + 1): - pp.SendEvent(np.asarray([missing_trigger_number & (self.max_trigger_counter - 1)], np.uint32)) + pp.SendEvent(np.asarray([np.bitwise_and(missing_trigger_number, self.max_trigger_counter_bits)], dtype=np.uint32)) self.data_error_occurred = False self.last_trigger_number = trigger_number else: logging.warning('Trigger number not increasing: read: %d, expected: %d', trigger_number, 0 if (self.last_trigger_number + 1 == self.max_trigger_counter) else (self.last_trigger_number + 1)) - self.last_trigger_number = (self.last_trigger_number + 1) & (self.max_trigger_counter - 1) + self.last_trigger_number = np.bitwise_and(self.last_trigger_number + 1, self.max_trigger_counter_bits) else: self.last_trigger_number = trigger_number - pp.SendEvent(self.remaining_data) + # inside if statement to ignore any data before first trigger + pp.SendEvent(self.remaining_data) + # outside if statement so that any data before first trigger becomes an event + # pp.SendEvent(self.remaining_data) self.remaining_data = item else: self.remaining_data = np.concatenate([self.remaining_data, item]) @@ -147,7 +157,8 @@ def handle_data(self, data, new_file=False, flush=True): # pp.StartingRun = True # set status and send BORE # starting run while join(timeout=1) == run_status.running: - if pp.Error or pp.Terminating or pp.StoppingRun: + if pp.Error or pp.Terminating: + logging.error("EUDAQ run %d forcibly stopped" % run_number) runmngr.cancel_current_run(msg="Run stopped by RunControl") status = join() logging.info("Run status: %s" % status) From d4b180cbdf56c8908b02b4e1c5b6b55de7fb3cf0 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 13:26:45 +0100 Subject: [PATCH 08/14] ENH: adding option to prevent EUDAQ producer form sending bad events --- pybar/daq/readout_utils.py | 9 +++++ pybar/scans/scan_eudaq_ext_trigger.py | 47 +++++++++++++++++++-------- 2 files changed, 42 insertions(+), 14 deletions(-) diff --git a/pybar/daq/readout_utils.py b/pybar/daq/readout_utils.py index 0dded0f34..854e7dc18 100644 --- a/pybar/daq/readout_utils.py +++ b/pybar/daq/readout_utils.py @@ -312,6 +312,15 @@ def is_data_record(value): return np.logical_and(np.logical_and(np.less_equal(np.bitwise_and(value, 0x00FE0000), 0x00A00000), np.less_equal(np.bitwise_and(value, 0x0001FF00), 0x00015000)), np.logical_and(np.not_equal(np.bitwise_and(value, 0x00FE0000), 0x00000000), np.not_equal(np.bitwise_and(value, 0x0001FF00), 0x00000000))) +def get_trigger_counter(value, mode=0): + '''Returns 31bit trigger counter (mode=0), 31bit timestamp (mode=1), 15bit timestamp and 16bit trigger counter (mode=2) + ''' + if mode == 2: + return np.right_shift(np.bitwise_and(value, 0x7FFF0000), 16), np.bitwise_and(value, 0x0000FFFF) + else: + return np.bitwise_and(value, 0x7FFFFFFF) + + def get_address_record_address(value): '''Returns the address in the address record. ''' diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index ac845658b..487178fc4 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -9,7 +9,7 @@ from pybar.run_manager import RunManager, run_status from pybar.scans.scan_ext_trigger import ExtTriggerScan -from pybar.daq.readout_utils import build_events_from_raw_data, is_trigger_word +from pybar.daq.readout_utils import build_events_from_raw_data, is_trigger_word, get_trigger_counter # set path to PyEUDAQWrapper sys.path.append('/path/to/eudaq/python/') @@ -34,13 +34,14 @@ class EudaqExtTriggerScan(ExtTriggerScan): "no_data_timeout": None, # no data timeout after which the scan will be aborted, in seconds "scan_timeout": None, # timeout for scan after which the scan will be stopped, in seconds "max_triggers": 0, # maximum triggers after which the scan will be stopped, if 0, no maximum triggers are set - "enable_tdc": False # if True, enables TDC + "enable_tdc": False, # if True, enables TDC + "send_bad_events": False # if True, send bad events where the trigger number has not increased by 1; if False, do not send these events } def scan(self): self.data_error_occurred = False self.last_trigger_number = None - # set TLU max trigger counter + # set TLU max trigger counter; EUDAQ TLU: 15bit trigger number self.max_trigger_counter = 2 ** 15 self.max_trigger_counter_bits = 2 ** np.int(np.ceil(np.log2(self.max_trigger_counter))) - 1 start = time() @@ -48,6 +49,7 @@ def scan(self): self.register_utils.set_command(lvl1_command) last_number_of_triggers = None self.remaining_data = np.zeros((0,), dtype=np.uint32) # initialize array of zero length + self.trigger_mode = self.dut['TLU']['TRIGGER_MODE'] with self.readout(no_data_timeout=self.no_data_timeout, **self.scan_parameters._asdict()): with self.trigger(): @@ -84,6 +86,7 @@ def handle_err(self, exc): self.data_error_occurred = True def handle_data(self, data, new_file=False, flush=True): + bad_event = False for data_tuple in data[0]: # only use data from first module events = build_events_from_raw_data(data_tuple[0]) # build events from raw data array for item in events: @@ -93,25 +96,41 @@ def handle_data(self, data, new_file=False, flush=True): if self.remaining_data.shape[0] > 0: # check trigger number if is_trigger_word(self.remaining_data[0]): - trigger_number = np.bitwise_and(self.remaining_data[0], self.max_trigger_counter_bits) + trigger_number = get_trigger_counter(self.remaining_data[0], mode=self.trigger_mode) + if trigger_number >= self.max_trigger_counter: + logging.warning('Trigger number larger than expected - read %d, maximum: %d' % (trigger_number, self.max_trigger_counter - 1)) if self.last_trigger_number is not None and ((self.last_trigger_number + 1 != trigger_number and self.last_trigger_number + 1 != self.max_trigger_counter) or (self.last_trigger_number + 1 == self.max_trigger_counter and trigger_number != 0)): if self.data_error_occurred: - if trigger_number > self.last_trigger_number: - missing_trigger_numbers = trigger_number - self.last_trigger_number - 1 - else: - missing_trigger_numbers = self.max_trigger_counter - (self.last_trigger_number - trigger_number) - 1 - logging.warning('Data errors detected: trigger number read: %d, expected: %d, sending %d empty events', trigger_number, 0 if (self.last_trigger_number + 1 == self.max_trigger_counter) else (self.last_trigger_number + 1), missing_trigger_numbers) - for missing_trigger_number in range(self.last_trigger_number + 1, self.last_trigger_number + missing_trigger_numbers + 1): - pp.SendEvent(np.asarray([np.bitwise_and(missing_trigger_number, self.max_trigger_counter_bits)], dtype=np.uint32)) + missing_trigger_numbers = [] + curr_missing_trigger_number = self.last_trigger_number + 1 + while True: + if curr_missing_trigger_number == self.max_trigger_counter: + curr_missing_trigger_number = 0 + if trigger_number == curr_missing_trigger_number: + break + missing_trigger_numbers.append(curr_missing_trigger_number) + curr_missing_trigger_number += 1 + logging.warning('Data errors detected - trigger number read: %d, expected: %d, sending %d empty events', trigger_number, self.last_trigger_number + 1, len(missing_trigger_numbers)) + for missing_trigger_number in missing_trigger_numbers: + pp.SendEvent(np.asarray([missing_trigger_number], dtype=np.uint32)) self.data_error_occurred = False self.last_trigger_number = trigger_number else: - logging.warning('Trigger number not increasing: read: %d, expected: %d', trigger_number, 0 if (self.last_trigger_number + 1 == self.max_trigger_counter) else (self.last_trigger_number + 1)) - self.last_trigger_number = np.bitwise_and(self.last_trigger_number + 1, self.max_trigger_counter_bits) + logging.warning('Trigger number not increasing - read: %d, expected: %d', trigger_number, self.last_trigger_number) + if self.send_bad_events: + self.last_trigger_number += 1 + if self.last_trigger_number == self.max_trigger_counter: + self.last_trigger_number = 0 + else: + bad_event = True else: self.last_trigger_number = trigger_number # inside if statement to ignore any data before first trigger - pp.SendEvent(self.remaining_data) + if bad_event: + logging.warning('Skipping event with trigger number %d', trigger_number) + bad_event = False + else: + pp.SendEvent(self.remaining_data) # outside if statement so that any data before first trigger becomes an event # pp.SendEvent(self.remaining_data) self.remaining_data = item From 35ef988d2cbb2b8435a4ed8bfa431e47d245f812 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 13:40:33 +0100 Subject: [PATCH 09/14] MAINT: rename function --- pybar/daq/readout_utils.py | 2 +- pybar/scans/scan_eudaq_ext_trigger.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pybar/daq/readout_utils.py b/pybar/daq/readout_utils.py index 854e7dc18..1744f0973 100644 --- a/pybar/daq/readout_utils.py +++ b/pybar/daq/readout_utils.py @@ -312,7 +312,7 @@ def is_data_record(value): return np.logical_and(np.logical_and(np.less_equal(np.bitwise_and(value, 0x00FE0000), 0x00A00000), np.less_equal(np.bitwise_and(value, 0x0001FF00), 0x00015000)), np.logical_and(np.not_equal(np.bitwise_and(value, 0x00FE0000), 0x00000000), np.not_equal(np.bitwise_and(value, 0x0001FF00), 0x00000000))) -def get_trigger_counter(value, mode=0): +def get_trigger_data(value, mode=0): '''Returns 31bit trigger counter (mode=0), 31bit timestamp (mode=1), 15bit timestamp and 16bit trigger counter (mode=2) ''' if mode == 2: diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index 487178fc4..3f35a6ae2 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -9,7 +9,7 @@ from pybar.run_manager import RunManager, run_status from pybar.scans.scan_ext_trigger import ExtTriggerScan -from pybar.daq.readout_utils import build_events_from_raw_data, is_trigger_word, get_trigger_counter +from pybar.daq.readout_utils import build_events_from_raw_data, is_trigger_word, get_trigger_data # set path to PyEUDAQWrapper sys.path.append('/path/to/eudaq/python/') @@ -96,7 +96,7 @@ def handle_data(self, data, new_file=False, flush=True): if self.remaining_data.shape[0] > 0: # check trigger number if is_trigger_word(self.remaining_data[0]): - trigger_number = get_trigger_counter(self.remaining_data[0], mode=self.trigger_mode) + trigger_number = get_trigger_data(self.remaining_data[0], mode=self.trigger_mode) if trigger_number >= self.max_trigger_counter: logging.warning('Trigger number larger than expected - read %d, maximum: %d' % (trigger_number, self.max_trigger_counter - 1)) if self.last_trigger_number is not None and ((self.last_trigger_number + 1 != trigger_number and self.last_trigger_number + 1 != self.max_trigger_counter) or (self.last_trigger_number + 1 == self.max_trigger_counter and trigger_number != 0)): From cce0159e75da887d0e9fc615a4dabe12bfc8ac3c Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 14:01:42 +0100 Subject: [PATCH 10/14] ENH: assume all trigger words are written, do not send mising events --- pybar/scans/scan_eudaq_ext_trigger.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index 3f35a6ae2..a1cac79a0 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -35,6 +35,7 @@ class EudaqExtTriggerScan(ExtTriggerScan): "scan_timeout": None, # timeout for scan after which the scan will be stopped, in seconds "max_triggers": 0, # maximum triggers after which the scan will be stopped, if 0, no maximum triggers are set "enable_tdc": False, # if True, enables TDC + "reset_rx_on_error": True, # if True, ignore RxSyncError, EightbTenbError from FEI4 receivers; if False, scan stops if any error is occurring "send_bad_events": False # if True, send bad events where the trigger number has not increased by 1; if False, do not send these events } @@ -83,7 +84,10 @@ def scan(self): def handle_err(self, exc): super(EudaqExtTriggerScan, self).handle_err(exc=exc) - self.data_error_occurred = True + # This is for debugging. + # Usually all trigger words are written and read out + # and events can be reconstructed and are sent to DataCollector + # self.data_error_occurred = True def handle_data(self, data, new_file=False, flush=True): bad_event = False From 24f32862913cf6e24dc13e1bd5037a46d3daaae4 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 15:19:23 +0100 Subject: [PATCH 11/14] REG: fix StoppingRun behaviorwq --- pybar/scans/scan_eudaq_ext_trigger.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index a1cac79a0..80c035db2 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -67,11 +67,10 @@ def scan(self): logging.info('Runtime: %s\nTriggers: %d\nData words/s: %s\n' % (strftime('%H:%M:%S', gmtime(time() - start)), triggers, str(data_words))) if self.max_triggers and triggers >= self.max_triggers: self.stop(msg='Trigger limit was reached: %i' % self.max_triggers) + if last_number_of_triggers is not None and last_number_of_triggers == self.dut['TLU']['TRIGGER_COUNTER']: # trigger number not increased, TLU has stopped + break # leave scan loop if last_number_of_triggers is not None or pp.StoppingRun: # stopping EUDAQ run - if last_number_of_triggers is None: - last_number_of_triggers = self.dut['TLU']['TRIGGER_COUNTER'] - elif last_number_of_triggers == self.dut['TLU']['TRIGGER_COUNTER']: # trigger number not increased, TLU has stopped - break # leave scan loop + last_number_of_triggers = self.dut['TLU']['TRIGGER_COUNTER'] if self.remaining_data.shape[0] > 0: pp.SendEvent(self.remaining_data) # send remaining event From 114eb169d8be9aba38f005b9a4d769690d00b38a Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 15:52:05 +0100 Subject: [PATCH 12/14] MAINT: rename attribute --- pybar/scans/scan_eudaq_ext_trigger.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/pybar/scans/scan_eudaq_ext_trigger.py b/pybar/scans/scan_eudaq_ext_trigger.py index 80c035db2..a310e2714 100755 --- a/pybar/scans/scan_eudaq_ext_trigger.py +++ b/pybar/scans/scan_eudaq_ext_trigger.py @@ -92,10 +92,10 @@ def handle_data(self, data, new_file=False, flush=True): bad_event = False for data_tuple in data[0]: # only use data from first module events = build_events_from_raw_data(data_tuple[0]) # build events from raw data array - for item in events: - if item.shape[0] == 0: + for event in events: + if event.shape[0] == 0: continue - if is_trigger_word(item[0]): + if is_trigger_word(event[0]): if self.remaining_data.shape[0] > 0: # check trigger number if is_trigger_word(self.remaining_data[0]): @@ -136,9 +136,9 @@ def handle_data(self, data, new_file=False, flush=True): pp.SendEvent(self.remaining_data) # outside if statement so that any data before first trigger becomes an event # pp.SendEvent(self.remaining_data) - self.remaining_data = item + self.remaining_data = event else: - self.remaining_data = np.concatenate([self.remaining_data, item]) + self.remaining_data = np.concatenate([self.remaining_data, event]) super(EudaqExtTriggerScan, self).handle_data(data=data, new_file=new_file, flush=flush) From ab3b609e6be326d0b383484a522d4c720fe11fd2 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 16:39:41 +0100 Subject: [PATCH 13/14] MAINT: adding Belle II Phase 1 commissioning run paper --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 9cd1598bb..63669d399 100644 --- a/README.md +++ b/README.md @@ -37,9 +37,9 @@ The features of the host software in Python: The pyBAR readout system was extensively used for various high-energy particle physics experiments as well as detector R&D. - Stave 0 demonstrator for the ATLAS High-Luminosity LHC (HL-LHC) upgrade at CERN (28 FEI4 chips): documentation in preparation - SHiP experiment at the CERN Super Proton Synchrotron (SPS) facility (24 FEI4 chips): documentation in preparation -- BEAST/FANGS experiment at the SuperKEKB facility (15 FEI4 chips): documentation in preparation +- BEAST/FANGS experiment at the SuperKEKB facility (15 FEI4 chips): DOI:[10.1016/j.nima.2018.05.071](https://doi.org/10.1016/j.nima.2018.05.071) - BEAST/TPC experiment at the SuperKEKB facility (8 FEI4 chips): documentation in preparation -- Detector tests for the ATLAS Diamond Beam Monitor (DBM): DOI: [10.1088/1748-0221/12/03/C03072](https://dx.doi.org/10.1088/1748-0221/12/03/C03072) +- Detector tests for the ATLAS Diamond Beam Monitor (DBM): DOI:[10.1088/1748-0221/12/03/C03072](https://dx.doi.org/10.1088/1748-0221/12/03/C03072) - Various other detector tests at [CERN SPS](http://sba.web.cern.ch) (Geneva, Switzerland), [DESY II](https://testbeam.desy.de) (Hamburg, Germany), and [ELSA](https://www-elsa.physik.uni-bonn.de) (Bonn, Germany) ## Installation From 5ec9f8801af5e0d400ea911f95ae587dcfab4329 Mon Sep 17 00:00:00 2001 From: Jens Janssen Date: Wed, 7 Nov 2018 16:42:13 +0100 Subject: [PATCH 14/14] PRJ: prepare for release v3.1.2 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 0e6b5ab95..ef538c281 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -3.1.2.dev0 +3.1.2