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As the LL/SC implementation preserved\nthe old value, the LSE implementation does likewise.\n\nSince commit:\n\n addfc38672c73efd (\"arm64: atomics: avoid out-of-line ll/sc atomics\")\n\n... the LSE and LL/SC implementations of cmpxchg are inlined as separate\nasm blocks, with another branch choosing between thw two. Due to this,\nit is no longer necessary for the LSE implementation to match the\nregister constraints of the LL/SC implementation. This was partially\ndealt with by removing the hard-coded use of x30 in commit:\n\n 3337cb5aea594e40 (\"arm64: avoid using hard-coded registers for LSE atomics\")\n\n... but we didn't clean up the hard-coding of x0, x1, and x2.\n\nThis patch simplifies the LSE implementation of cmpxchg, removing the\nregister shuffling and directly clobbering the 'old' argument. This\ngives the compiler greater freedom for register allocation, and avoids\nredundant work.\n\nThe new constraints permit 'old' (Rs) and 'new' (Rt) to be allocated to\nthe same register when the initial values of the two are the same, e.g.\nresulting in:\n\n\tCAS\tX0, X0, [X1]\n\nThis is safe as Rs is only written back after the initial values of Rs\nand Rt are consumed, and there are no UNPREDICTABLE behaviours to avoid\nwhen Rs == Rt.\n\nThe new constraints also permit 'new' to be allocated to the zero\nregister, avoiding a MOV in a few cases. The same cannot be done for\n'old' as it is both an input and output, and any caller of cmpxchg()\nshould care about the output value. Note that for CAS* the use of the\nzero register never affects the ordering (while for SWP* the use of the\nzero regsiter for the 'old' value drops any ACQUIRE semantic).\n\nCompared to v6.2-rc4, a defconfig vmlinux is ~116KiB smaller, though the\nresulting Image is the same size due to internal alignment and padding:\n\n [mark@lakrids:~/src/linux]% ls -al vmlinux-*\n -rwxr-xr-x 1 mark mark 137269304 Jan 16 11:59 vmlinux-after\n -rwxr-xr-x 1 mark mark 137387936 Jan 16 10:54 vmlinux-before\n [mark@lakrids:~/src/linux]% ls -al Image-*\n -rw-r--r-- 1 mark mark 38711808 Jan 16 11:59 Image-after\n -rw-r--r-- 1 mark mark 38711808 Jan 16 10:54 Image-before\n\nThis patch does not touch cmpxchg_double*() as that requires contiguous\nregister pairs, and separate patches will replace it with cmpxchg128*().\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \nCc: Catalin Marinas \nCc: Peter Zijlstra \nCc: Robin Murphy \nCc: Will Deacon \nLink: https://lore.kernel.org/r/20230314153700.787701-2-mark.rutland@arm.com\nSigned-off-by: Will Deacon ","shortMessageHtmlLink":"arm64: atomics: lse: improve cmpxchg implementation"}},{"before":"d1a505416340607857bfbcc0a1d0765a7919c57a","after":"726f9193d2e4d447ba6938fa797caf801115672a","ref":"refs/heads/lineage-21.0","pushedAt":"2024-07-13T10:22:40.000Z","pushType":"push","commitsCount":8,"pusher":{"login":"Inkypen79","name":"Nicholas Magill","path":"/Inkypen79","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/42582720?s=80&v=4"},"commit":{"message":"arm64: atomics: lse: improve cmpxchg implementation\n\nFor historical reasons, the LSE implementation of cmpxchg*() hard-codes\nthe GPRs to use, and shuffles registers around with MOVs. This is no\nlonger necessary, and can be simplified.\n\nWhen the LSE cmpxchg implementation was added in commit:\n\n c342f78217e822d2 (\"arm64: cmpxchg: patch in lse instructions when supported by the CPU\")\n\n... the LL/SC implementation of cmpxchg() would be placed out-of-line,\nand the in-line assembly for cmpxchg would default to:\n\n\tNOP\n\tBL\t\n\tNOP\n\nThe LL/SC implementation of each cmpxchg() function accepted arguments\nas per AAPCS64 rules, to it was necessary to place the pointer in x0,\nthe older value in X1, and the new value in x2, and acquire the return\nvalue from x0. The LL/SC implementation required a temporary register\n(e.g. for the STXR status value). As the LL/SC implementation preserved\nthe old value, the LSE implementation does likewise.\n\nSince commit:\n\n addfc38672c73efd (\"arm64: atomics: avoid out-of-line ll/sc atomics\")\n\n... the LSE and LL/SC implementations of cmpxchg are inlined as separate\nasm blocks, with another branch choosing between thw two. Due to this,\nit is no longer necessary for the LSE implementation to match the\nregister constraints of the LL/SC implementation. This was partially\ndealt with by removing the hard-coded use of x30 in commit:\n\n 3337cb5aea594e40 (\"arm64: avoid using hard-coded registers for LSE atomics\")\n\n... but we didn't clean up the hard-coding of x0, x1, and x2.\n\nThis patch simplifies the LSE implementation of cmpxchg, removing the\nregister shuffling and directly clobbering the 'old' argument. This\ngives the compiler greater freedom for register allocation, and avoids\nredundant work.\n\nThe new constraints permit 'old' (Rs) and 'new' (Rt) to be allocated to\nthe same register when the initial values of the two are the same, e.g.\nresulting in:\n\n\tCAS\tX0, X0, [X1]\n\nThis is safe as Rs is only written back after the initial values of Rs\nand Rt are consumed, and there are no UNPREDICTABLE behaviours to avoid\nwhen Rs == Rt.\n\nThe new constraints also permit 'new' to be allocated to the zero\nregister, avoiding a MOV in a few cases. The same cannot be done for\n'old' as it is both an input and output, and any caller of cmpxchg()\nshould care about the output value. Note that for CAS* the use of the\nzero register never affects the ordering (while for SWP* the use of the\nzero regsiter for the 'old' value drops any ACQUIRE semantic).\n\nCompared to v6.2-rc4, a defconfig vmlinux is ~116KiB smaller, though the\nresulting Image is the same size due to internal alignment and padding:\n\n [mark@lakrids:~/src/linux]% ls -al vmlinux-*\n -rwxr-xr-x 1 mark mark 137269304 Jan 16 11:59 vmlinux-after\n -rwxr-xr-x 1 mark mark 137387936 Jan 16 10:54 vmlinux-before\n [mark@lakrids:~/src/linux]% ls -al Image-*\n -rw-r--r-- 1 mark mark 38711808 Jan 16 11:59 Image-after\n -rw-r--r-- 1 mark mark 38711808 Jan 16 10:54 Image-before\n\nThis patch does not touch cmpxchg_double*() as that requires contiguous\nregister pairs, and separate patches will replace it with cmpxchg128*().\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \nCc: Catalin Marinas \nCc: Peter Zijlstra \nCc: Robin Murphy \nCc: Will Deacon \nLink: https://lore.kernel.org/r/20230314153700.787701-2-mark.rutland@arm.com\nSigned-off-by: Will Deacon ","shortMessageHtmlLink":"arm64: atomics: lse: improve cmpxchg implementation"}},{"before":"dec7cfe09dfece1f03217d51329b017cdcc4fe96","after":"d1a505416340607857bfbcc0a1d0765a7919c57a","ref":"refs/heads/lineage-21.0","pushedAt":"2024-07-13T09:54:38.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Inkypen79","name":"Nicholas Magill","path":"/Inkypen79","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/42582720?s=80&v=4"},"commit":{"message":"ANDROID: extract-cert: omit PKCS#11 support if building against BoringSSL\n\nBoringSSL does not implement the ENGINE API. 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